1. Introduction

Neural stimulators have been applied to treat various neural disorders such as in retinal implants to treat sight impairment and in deep brain stimulation devices to suppress epileptic seizures ^{[1- 3]}. A stimulator circuit should deliver and recover electric charge in a precisely controlled fashion between the electrical device and the target tissue so that it is able to initiate an action potential leading to events such as sensory perception without causing damage to the tissue.

Among several important requirements for the stimulator design, the stimulator should achieve high voltage compliance so that the stimulator is able to deliver wide range of desired current to the high impedance electrode-tissue interface. The stimulator is thus usually designed with high-voltage (HV) CMOS or DMOS transistors as HV supply is needed to meet the voltage compliance requirement ^[1]. Low voltage (LV) standard CMOS implementations have previously been presented with low supply voltages, but these works have limitations in maximum deliverable current ^{[3, 4]}.

Another key requirement is safety as maintaining charge balance during the stimulation process is important to prevent tissue damage. Thus, biphasic current stimulation is usually used in which the charge is delivered to the tissue in the first phase and is recovered back in the next phase. Ideally, there should be no charge remaining in the tissue after each stimulation cycle. However, mismatch in the biphasic pulse due to process variations result in a non-ideal stimulation and may cause some residual charge to remain in the tissue. This net charge builds a voltage difference between the electrodes, and ultimately can lead to tissue damage. Several charge balancing methods have been proposed in previous works such as DC block capacitor ^[5], electrode shorting ^[1] and active charge balancing ^{[6, 7]} to alleviate this issue. DC blocking is not appropriate for multi-channel applications as it requires a large external capacitor per electrode. Electrode shorting is a simple method but takes a long time to sufficiently short out the residual charge. Active charge balancing in ^[6] utilizes a complex feedback circuitry with HV comparator which requires a HV process.

In this paper, in comparison to previous similar works ^{[1, 4, 6, 7]}, a current-mode bipolar neural stimulator IC is proposed whose output current driver is composed of stacked 3.3-V LV standard CMOS transistors with dynamic gate biasing circuit in order to reliably operate at high voltage supply and deliver from 32 µA up to 992 µA of current to the target tissue. A regulated cascode output stage for boosting the output impedance of the current driver is used in order to improve the stimulation accuracy. Additionally, the proposed stimulator is equipped with a simple feedback-based active charge balancing circuit in order to achieve minimal residual charge after stimulation for safety requirement. All the block level circuits comprising the overall stimulator are designed using LV transistors. Section II describes the architecture and general design considerations. The circuit design details are presented in Section III. The simulation results are reported in Section IV, followed by the conclusions in Section V.

2. Design Considerations and System Architecture

There are several specifications that need to be defined when designing the stimulator. Some of these parameters include stimulation waveform, pulse width, repetition rate, and current magnitude range. A biphasic rectangular waveform is considered for stimulation with a 100-µs stimulation pulse width, 20-µs interphasic delay between cathodic and anodic pulses, and repetition rate of 400 µs. After the initial stimulation phase, charge balancing phase takes place within the 50-µs short timing window. This work targets current magnitudes in the range of 32 µA to 992 µA which is sufficient to support various applications such as retinal implants and for treating epilepsy. Fig. 1 shows the equivalent electrical model ^[2] of the electrode and tissue interface used in the design. In order to accurately deliver up to around 1 mA of current to a 10-kΩ load, a high supply voltage is required in the output driver circuit. In this work, 12.8-V supply is chosen with margin considering the voltage drop in the switches and the current sink transistor in the output driver ^[8].

Fig. 1. Equivalent electrical model of electrode-tissue interface used in the design.

Fig. 2 shows the overall block diagram of the proposed neural stimulator architecture which is comprised of the following building blocks; 5-bit digital-to-analog converter (DAC), digital control logic, level-shifters, output current driver, and charge balancing circuits. The DAC provides current amplitude values from 4 to 124 µA, while the digital control logic is responsible for controlling the output current amplitude, timing of the waveforms, and the charge balancer circuit. The level-shifters are required to convert the 0-3.2 V trigger signal to 9.6-12.8 V signal to drive the PMOS transistor switch of the output current driver. The output of the DAC is applied to the current driver, in which the current is ultimately amplified by 8 times through current mirroring in order to provide up to a maximum of 992 µA stimulation current. The final component is the simple active charge balancing circuit that ensures minimal net charge remaining in the tissue. The charge balancer first senses the voltage difference between the two electrodes. If the difference exceeds the safety range of -50 mV to +50 mV ^[6], the charge balancing circuit sends a feedback signal to the digital control logic so that the current driver is controlled to generate additional cathodic or anodic current in order to reduce the voltage difference between the electrodes. The charge balancer keeps sending feedback to the control logic until the voltage difference between the two electrodes is lower than 50 mV. Thus, the residual charge would be sufficiently small enough to prevent tissue damage. In addition to the active charge balancer function, the electrode shorting option can be employed to support residual charge reduction after each stimulation cycle. The shorting technique is also controlled by the digital control logic, which shunts two electrodes in order to force the voltage between them to be equal to zero.

Fig. 2. Overall architecture of neural stimulator IC.

3. Circuit Design

Fig. 3 presents the simplified block diagram of the output current driver. A bipolar H-bridge topology is employed in which two switches diagonally opposite to each other are turned ON in each phase to produce the biphasic current waveform. Due to HV operation of the output current driver, a HV transistor switch is commonly utilized. In this work, each HV switch transistor is replaced by a stack of four standard CMOS transistors as depicted in Fig. 4. Each standard transistor has the nominal operation voltage of 3.3 V, and the voltage difference between any of its terminals is designed so that it would not exceed the nominal voltage to avoid device breakdown. Thus, the dynamic gate biasing topology ^[9] is utilized in order to ensure all the transistors work within the nominal voltage during transient operation. Since the PMOS transistor switch requires 9.6–12.8 V control signal, level-shifters are provided in order to produce this signal.

Fig. 3. Block diagram of biphasic bipolar H-bridge output current driver.

Fig. 4. Circuit schematic of proposed output current driver.

The basic operation of the output driver in Fig. 4 is described as follows; IN_P1,2 and IN_N1,2 are the control signals which control the ON and OFF of the switch transistors. 3.2 V, 6.4 V, and 9.6 V are fixed DC voltages which can be generated internally ^[8] or applied externally. In order to turn OFF the upper switch (HSW1) and turn ON the lower switch (HSW2), the IN_P1 must be set to 12.8 V, while the IN_N1 must be 3.2 V. This turns the transistor M_N1 ON. As a result, the source of M_N2 is shorted to the current sink, and the transistor M_N2 would turn ON as its gate is constantly biased to 3.2 V. When M_N2 is ON, the node n1 is connected to the current sink, which means this node goes ‘LOW’ causing M_BP1 to turn ON. Thus, the gate of M_N3 is shorted to 3.2 V allowing the transistor M_N3 to turn ON. Similar sequence of events occurs, and results in transistor M_N4 to turn ON. Finally, the switch HSW2 is ON since every NMOS transistor of its stack is active. On the other hand, INP1 is set to be 12.8 V which turns OFF M_P1. M_P2 is also OFF because its gate is constantly biased at 9.6 V. Moreover, when the gate of M_N4 is shorted to 3.2 V, transistor M_P4 is OFF as its drain is connected to a ‘LOW’ voltage. At the same time, M_BN3 is OFF and M_BP3 is ON which makes the gate voltage of MP3 to be 6.4 V. This turns OFF M_P3. As a result, the switch HSW1 is OFF since every PMOS transistor of its stack is OFF. Similarly, the same mechanism would occur to turn ON all the transistors of the upper stack and turn OFF those of the lower one in case when the upper switch is turned ON and the lower switch is turned OFF.

The current sink part of the current driver in Fig. 4 is designed using a regulated cascode topology ^[10] in order to enhance the output impedance as depicted in Fig. 5. A differential amplifier A_DA is applied to equalize the drain-source voltage values of V_DS1 and V_DS2. This makes V_GS and V_DS of the two mirror transistors M₁ and M₂ equal to each other. The differential amplifier is composed of a differential pair that consists of M₅ and M₆, followed by a DC-level shifter M₇. When transistors M₂ and M₄ are in saturation mode, the output resistance of the current sink is determined by

where A_DA is the gain of the differential amplifier, and A_V-M4 denotes the gain of the cascode transistor M₄ which is computed as A_V-M4 = g_m4r₀₄. Therefore, the output impedance is boosted to a higher value in comparison to a simple current mirror circuit.

Fig. 5. Circuit schematic of current sink in the output driver.

The DAC, shown in Fig. 6, is designed to generate current whose amplitude varies from 4 to 124 µA. A cascode current-steering topology is utilized to construct the DAC in order to achieve high linearity ^[11].

Fig. 6. Circuit schematic of DAC.

After every stimulation cycle, there is some residual charge accumulated in the electrodes due to the mismatch in the circuit. This residual charge leads to the increment of the voltage difference between the two electrodes. Therefore, the designed active charge balancer operates based on that output differential voltage. At first, the charge balancer circuit initially determines the voltage difference between the two electrodes. If the voltage difference is smaller than 50 mV, no feedback signal is sent back to the digital controller. In case the voltage difference exceeds 50 mV, the charge balancer delivers a feedback signal to the digital controller to produce additional cathodic or anodic current in order to minimize the voltage difference between the electrodes.

Fig. 7. Simplified block diagram of active charge balancer.

Fig. 7 shows the simplified block diagram of the active charge balancer, and explains its principle. If the voltage of the electrode 1 is 50 mV greater than that of the electrode 2 (EL₁ > EL₂), the feedback signal would be sent to make the digital controller generate more current whose direction would be from electrode 2 to electrode 1 in order to lessen the accumulated charge. Similarly, if voltage of the electrode 1 is 50-mV smaller (EL₁ < EL₂), an additional opposite-direction current would be generated. The charge balancer continues sending feedback until the voltage difference becomes lower than 50 mV.

4. Simulation Results

The proposed stimulator IC is designed using 0.18-µm standard CMOS process. The layout capture of the overall IC is shown in Fig. 8. The core layout area excluding the metal routing paths is 0.12 mm². Fig. 9 shows the stimulation transient voltage waveform. Some mismatch between the cathodic and anodic waveforms is added on purpose to the pulse width to observe the operation of the charge balancing circuit. It can be observed that a large initial voltage difference is reduced below 50 mV after charge balancing. Fig. 10 shows the simulated stimulus output current versus the output voltage for the four different DAC input values. The voltage compliance at the maximum reachable current is approximately 12.4 V, which is 96.8% of the supply voltage.

Fig. 8. Layout capture of designed neurostimulator IC.

Fig. 9. Stimulation output voltage waveform with charge balancer in operation.

Fig. 10. Simulated output current for selected DAC codes.

Fig. 11 (a) depicts the cathodic and anodic currents of the proposed stimulator with respect to the DAC input codes. The output current varies with a step of 32 µA (1 LSB current of the DAC) to 992 µA (full scale current of the DAC). According to the result, the dissimilarity between the cathodic and anodic currents is negligibly small, as shown in Fig. 11 (b).

Fig. 11. (a) Cathodic and anodic current versus DAC input codes. (b) Mismatch between cathodic and anodic current versus DAC input codes.

Regarding the power consumption, the total static power consumed by the IC is 0.7 mW, which is due to the operation of the current DAC, current mirror, and charge balancing circuits.

Table 1 summarizes the performance of the proposed stimulator, and compares them with those from other previous works. Despite using a low-voltage standard CMOS process, the stimulator in this work is able to accurately deliver a wide range of current to a high impedance load.

5. Conclusion

A charge balanced biphasic neurostimulator circuit which has the ability to deliver up to 1-mA current through 10-kΩ load using 12.8 V supply voltage is designed using 180-nm standard CMOS process. The proposed stimulator employs a transistor-stacked output current driver architecture for reliable high voltage operation and achieves a voltage compliance of 12.4 V by using a regulated cascode current mirror topology. For future work, benchtop testing and in-vitro measurements will be carried out to verify the performance of the IC.