| Title |
An Implantable Charge Balanced Neurostimulator IC Using Standard CMOS Process |
| Authors |
(Tuan Vo) ; (Hyouk-Kyu Cha) |
| DOI |
https://doi.org/10.5573/IEIESPC.2026.15.4.591 |
| Keywords |
Neural stimulation; Active charge balancing; Transistor stacking; Dynamic biasing |
| Abstract |
This paper presents the design of a bipolar current-mode stimulator integrated circuit (IC) for implantable prosthetic devices using 0.18-μm standard CMOS process. The proposed stimulator IC is capable of delivering up to 1-mA current through 10-kΩ load using 12.8 V supply voltage. The output impedance of the stimulator is enhanced by utilizing a regulated cascode output current driver stage, which achieves a voltage compliance of 12.4 V. In order to allow low-voltage standard transistors to operate reliably at high voltage, transistor stacking and dynamic gate biasing techniques are used. In addition, a simple active charge balancing circuit is included to achieve minimal net charge after stimulation cycle is complete. The overall layout area is 0.12 mm2 . |