1. Introduction

Modern signal processing applications emerging in the telecommunications and instrumentation industries need high-speed and high-resolution analog-to-digital converters (ADCs). Time-interleaved ADCs (TIADCs) provide an effective way to achieve high sampling rate while maintaining high resolution ^[1]. However, fabrication errors result in a variety of channel mismatch errors, limiting the conversion precision of TIADC. The main mismatches are offset, gain, timing, and bandwidth mismatches. Bandwidth mismatch can be eliminated in the process of timing mismatch and gain mismatch elimination. These mismatches generate spurs in the output spectrum and significantly reduce the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of a TIADC system.

There are many calibration techniques for TIADC channel mismatch errors, which can be divided into analog calibration, mixed calibration, and all-digital calibration ^[2]. Compared with the other two techniques, the all-digital calibration technique is more robust and portable under different processes. At the same time, it can also take full advantage of the cost and integration advantages brought by the progress of integrated circuit technology in digital circuits.

All-digital TIADC calibration techniques mainly include methods based on a fractional delay filter ^[3], the Taylor formula ^[4], a reference channel ^[5], modulation ^[6-8], and so on. The first two calibration techniques require a complex filter structure under high-precision compensation. The method based on a reference channel is very effective, but the introduction of an extra reference channel greatly increases the complexity, and a reference-channel ADC usually works at speed that does not match the speed of the sub-ADC of TIADC, thus introducing additional bandwidth mismatch ^[9].

In contrast, the modulation calibration algorithm has high calibration accuracy and low complexity. However, when the input signal frequency is ${\lambda}$fs/2M, where M is the number of channels, and fs is sampling frequency (${\lambda}$=0,1…M-1), channel mismatch errors are often difficult to estimate and calibrate, and they may even cause deterioration of the output. To solve this problem, one study introduced a notch filter to trap a special-frequency signal so that the output would not be wrong, but the mismatch error could not be calibrated ^[6].

Digital Down Conversion (DDC) is an important part of a high-speed TIADC acquisition system. Its main function is to convert a digitized real signal centered at an intermediate frequency to a base-band complex signal centered at zero frequency. It is also used to reduce the input signal to a lower sampling rate, thus allowing lower-speed processors to process fast incoming signals. At present, there are mainly two methods to implement DDC. The first is utilizing a DDC device, which features advantages of convenient use and outstanding performance. However, its disadvantage of narrow-band imposes restrictions on engineering application.

Another method is DDC implementation in a field programmable gate array (FPGA), which features high operating speed, parallel processing, lower resource cost, high flexibility, fast IO speed, etc. Therefore, an FPGA is especially suitable for broadband digital processing. As FPGAs develop at high speed, they make great strides in device speed and inner resources. However, there is still considerable speed and resource pressure for some DDC architectures (for instance, the traditional serial architecture ^[10,11], the polyphase filtering-based broadband DDC architecture ^[12-16], and so on).

In this work, a digital post-processing circuit for high-speed high-resolution TIADC is proposed, which contains a modulation calibration circuit suitable for any frequency and a DDC circuit with optional decimation ratios of 1, 2, 4, and 8 times.

The rest of this paper is structured as follows. Section II describes the principles of the modulation calibration algorithm and the reason why a traditional modulation algorithm cannot be calibrated at some special frequencies. Sections III and IV present the design of a calibration circuit and DDC circuit in detail. Finally, Section V shows the simulation and experiment results of the proposed digital post-processing circuit, and Section VI gives the conclusion.

2. Background

2.1 Principle of Modulation Calibration Technique

In a TIADC, the spectrum generated by offset mismatch is located at $kf_{s}/M$, and the spectrum generated by gain and timing mismatch is located at $\pm f_{in}+kf_{s}/M$, where M is the number of channels, k is an integer not bigger than M, and f$_{in}$ is the frequency of input signal. The basic theory of the modulation calibration technique is to use the position characteristics of the TIADC mismatch errors on the spectrum and to construct a signal with the same position as each spurious spectrum. The constructed signal is called a pseudo-spurious signal. The calibration can be achieved by multiplying the signal by an appropriate estimated coefficient and then making a difference between the signal to be calibrated and the pseudo-spurious signal, thus eliminating the spurs due to channel mismatch.

Taking a four-channel TIADC system as an example, the modulation process can be implemented using a Walsh function. The first four sequences of the Walsh function vary periodically is as follows:

(1)

$ Wal_{i}\left(n\right)=\left\{\begin{array}{lllll} 1 & 1 & 1 & 1, & \left(i=0\right)\\ 1 & 1 & -1 & -1, & \left(i=1\right)\\ 1 & -1 & 1 & -1, & \left(i=2\right)\\ 1 & -1 & -1 & 1, & \left(i=3\right) \end{array}\right. $

When a signal is multiplied by the Walsh function, the signal spectrum is shifted by 0, f$_{\mathrm{s}}$/4, f$_{\mathrm{s}}$/2, and 3f$_{\mathrm{s}}$/4 in the frequency domain. Using this property, we can construct a pseudo-spurious signal.

For gain and timing mismatch errors, the pseudo-spurious signal can be realized by multiplying the output of the TIADC with a Walsh function, while for offset mismatch error, the Walsh function itself can be used as a pseudo-spurious signal. We assume ${\alpha}$ is the estimation coefficient, which can be obtained by performing correlation operations on signals before and after modulation. Then, the calibrated output of TIADC is:

(2)

$ \hat{y}\left[n\right]=y\left[n\right]-\alpha y_{e}\left[n\right] $

where $\hat{y}\left[n\right]$ is the signal after calibration, $y\left[n\right]$ is the output of the TIADC that needs to be calibrated, $y_{e}\left[n\right]$ is the pseudo-spurious signal, and $y_{e}^{'}\left[n\right]$ is the derivative of pseudo-spurious signal. Assuming ${\alpha}$$_{ti}$, ${\alpha}$$_{gi}$, and ${\alpha}$$_{oi}$ are the error estimation coefficients for timing, gain, and offset, respectively, for a four-channel TIADC, the calibrated output is:

(3)

$$ \begin{aligned} \hat{y}[n]=y[n]-\underbrace{y_{e 1}^{\prime}[n] \cdot \alpha_{t 1}-y_{e 2}^{\prime}[n] \cdot \alpha_{t 2}-y_{e 3}^{\prime}[n] \cdot \alpha_{t 3}}_{\text {ti ming mismatch }} \\ \underbrace{-y_{e 1}[n] \cdot \alpha_{g 1}-y_{e 2}[n] \cdot \alpha_{g 2}-y_{e 3}[n] \cdot \alpha_{g 3}}_{\text {gain mismatch }} \\ \underbrace{-O_{e 1} \cdot \alpha_{o 1}-O_{e_2} \cdot \alpha_{o 2}-O_{e_3} \cdot \alpha_{o 3}}_{\text {offset mismatch }} \\ \end{aligned} $$

(4)

$ \left\{\begin{array}{l} y_{ei}\left[n\right]=Wal_{i}\cdot y\left[n\right]\\ y_{ei}^{'}\left[n\right]=Wal_{i}\cdot y'\left[n\right]\\ O_{ei}\left[n\right]=Wal_{i}\left[n\right] \end{array}\right.~ ~ ~ ~ ~ ~ ~ ~ ~ i=1,2,3 $

The modulation calibration block diagram is shown in Fig. 1. The output of the TIADC is first modulated by the Walsh function to construct a quadrature signal, and then the correlation results of the quadrature signals with mismatch errors are used to estimate the value of errors. Fig. 2 shows the specific estimation process of the timing and gain errors. The corresponding estimated error coefficients are as follows:

(5)

$ \left\{\begin{array}{l} \alpha _{ti}\left(n+1\right)=\alpha _{ti}\left(n\right)+\mu _{t}\left(y\left[n\right]\times y_{ei}^{'}\left[n\right]\right)\\ \alpha _{gi}\left(n+1\right)=\alpha _{gi}\left(n\right)+\mu _{g}\left(y\left[n\right]\times y_{ei}\left[n\right]\right)\\ \alpha _{oi}\left(n+1\right)=\alpha _{oi}\left(n\right)+\mu _{o}\left(y\left[n\right]\times o_{ei}\left[n\right]\right) \end{array}\right.\,\,\,\,\,i=1,2,3 $

In (5), ${\mu}$$_{t}$, ${\mu}$$_{g}$, and ${\mu}$$_{o}$ signify the iteration steps of timing, gain, and offset mismatch, and the value of iteration step size depends on the tradeoff between calibration accuracy and speed. It should be noted that although the gain and timing mismatch errors are in the same position on the spectrum, their phases are not the same. Thus, for timing mismatch calibration, the input signal needs to be differentiated.

Fig. 1. The traditional modulation calibration structure.

Fig. 2. The estimation process of timing and gain mismatch errors.

2.2 Analysis of Calibration Failure at Some Special Frequencies

The principle of the modulation calibration technique is to construct a pseudo-signal that has the same position with spurs due to mismatch error. However, at some special frequencies, the spurious signals coincide with the input signal. Thus, channel mismatch errors cannot be estimated. When the input signal satisfies (6), the signal frequency will be aliased with the spurious generated by timing and gain mismatch errors. When the input signal satisfies (7), the signal will be aliased with spurious generated by offset mismatch error.

(6)

$ f_{in}=\pm f_{in}+kf_{s}/M \\ $

(7)

$ f_{in}=kf_{s}/M $

Taking a four-channel TIADC as an example, in the first Nyquist band, the special frequency points that conform to (6) are 0.125f$_{s}$, 0.25f$_{s}$, and 0.375f$_{s}$. Taking f$_{in}$=0.125f$_{s}$ as an example, the spectrum with timing mismatch error is shown in Fig. 3(a). The partial gain and timing mismatch spurs coincide with the input signal spectrum. When the input signal in the first Nyquist band is at 0.25f$_{s}$ and satisfies (7), the signal spectrum will be aliased with the spurious spectrum of offset mismatch error as shown in Fig. 3(b).

To solve this deficiency, the traditional algorithm uses a notch filter to filter these special frequency points to avoid further deterioration after calibration, but these errors are not eliminated. Further, the cutoff frequency of the notch filter is normally not ideal. As a result, signals near the special frequency cannot be calibrated either. Therefore, better solutions need to be considered.

Fig. 3. The spectrum of the input signal at a special frequency.

3. Proposed Calibration Technique

In order to overcome the shortcomings of traditional modulation algorithms that cannot be calibrated at special frequency points, the proposed calibration technique has a test signal before the actual signal that is pre-input to the TIADC. The estimated mismatch errors are stored. Then, with an arbitrary actual signal input, a method based on threshold judgment is used to determine whether it is at a special frequency or not. When the system detects that the input signal is at a special frequency, the stored errors are directly extracted for compensation; otherwise, a background adaptive digital calibration algorithm executes in real time. The overall calibration system after optimization is shown in Fig. 4. A memory module is used to save the error estimation value obtained by a test signal.

The principle of frequency detection based on threshold judgment is shown in Fig. 5. For a better explanation, we take a four-channel TIADC as an example. When the input signal is located at 0.125f$_{s}$ or 0.375f$_{s}$, the absolute value of the TIADC output has the same size as the output after 8 cycles; that is, the long-term average of (1-z$^{-8}$) for the output should be approximately zero. For signals near these two frequencies, the farther away from these special frequency points they are, the greater the difference in their long-term average will be.

Also, for an input signal located at f$_{s}$/4, the value of the sampling signal should be the same in each cycle, so the difference between the current signal and the signal after 8 cycles should also be approximately zero. By extension, for a TIADC with M=2$^{\mathrm{n}}$ (n=1, 2, …) channels, the expression of threshold judgment can be expressed as follows:

where A is the threshold value. Considering the influence of noise and other factors, the threshold value will not be exactly equal to 0.

After repeating testing with multiple samples, in our four-channel TIADC, the maximum threshold value was about 0.06. Therefore, in this work, the threshold value was set to 0.06. When the threshold value is less than the set value, the calibration module directly compensates for the stored error value. When the threshold value is larger than the set value, the calibration module executes the background calibration. In this way, the problem of not being able to calibrate at special frequency points can be solved.

In the process of calibration algorithm implementation, the hardware complexity of the multiplier is much higher. Therefore, reducing the number of multipliers in the algorithm can greatly reduce the hardware overhead of the whole calibration system. Since the modulation process of the Walsh function can be viewed as a periodic variation of the signal amplitude, the involvement of multipliers is not required. Therefore, redundant terms can be resolved by sharing the same input terms. By extracting the same input terms of (3), it can be transformed into (9) as follows:

After optimization, both gain and timing calibration processes require only one multiplier, as shown in Fig. 4. After this optimization, the number of multipliers does not increase with the number of channels of the TIADC. The error estimation module can be further optimized by changing the order of signal correlation and modulation as shown in Fig. 6.

For the estimation of timing mismatch, a derivation is needed. Here, a delay unit is utilized to replace the traditional derivation module to reduce the complexity of the estimation module. The reason can be explained as follows. When there is a timing mismatch error, the digital output $\hat{y}\left[n\right]$ would have a different phase with its delay, so the correlation result will not be zero. Thus, the timing mismatch error can be realized by a correlation operation, which can be obtained by an AVE&LMS calculation.

Filters are the most powerful module in the calibration system. Thus, in this work, we introduce CSD coding combined with Horner’s rule and sub-expression sharing to optimize the complexity. The CSD coding is the conversion of a contiguous 1 sequence of length greater than 2 in the complement into a form of 100... 0 (-1), where (-1) indicates that the bit is negative. For example, when the input data is a five digit complement 00111, it can be converted to the form 0100 (-1). Thus, the non-zero bits in the filter coefficients are minimized, thereby reducing the complexity of multiplication. After CSD coding, the order of shifting and adding during the operation can be adjusted by Horner’s rule. The whole process is shown in Fig. 7.

When the input is x, we take a data width of 8 bits as an example. For one group of the multiplication and accumulation operations, 2$^{-5}$x+2$^{-3}$x, only the high 5 bits of x participate in the operation. When the accumulation method is changed by Horner's rule, the result becomes 2$^{-5}$x+2$^{-3}$x=2$^{-3}$ (x+2$^{-2}$x). At this time, the whole data width of x is involved in the operation, which improves the precision of multiplication. On the other hand, a sub-expression sharing based on the transposed FIR filter is introduced by having the term that occurs more frequently as a common term and multiplies the input signal. Then, the output of the constant coefficient multiplier in the filter is constructed by adding shifts, so the amount of operation in the multiplication process can be reduced. As shown in Fig. 4, the Hilbert filter and the derivative filter have the same input terms, so it is also possible to optimize the two filters together, extract the same sub-expression, and use a set of sharing sub-expressions.

The optimized Hilbert filter and derivative filter are shown in Fig. 8, where ">>>" means the shift logic right of a signed number. The common sub-expressions of the two filters are 101, 101, 1001, 100(-1), 10001, and 1000(-1), and the corresponding logical relationship is shown in (10).

Fig. 4. Architecture of the proposed calibration technique.

Fig. 5. The proposed judgment structure of threshold.

Fig. 6. Architecture of the proposed mismatch estimation.

Fig. 7. The principle of Horner’s rule.

Fig. 8. Architecture of the proposed improved Hilbert filter and derivative filter.

4. Design of DDC Circuit

Due to the high-speed and high-precision characteristics of the TIADC, the data rate after conversion is too fast, so a DDC system is need to better match the rate requirements of the subsequent receiving devices. The proposed DDC system is shown in Fig. 9, and it consists of a Numerically Controlled Oscillator (NCO), a mixer, a low-pass filter (LPF), and so on. The functions of the DDC in this design include frequency modulation, optional multiple decimation by a factor of 1, 2, 4, and 8, as well as gain and complex-to-real conversion.

The NCO is used to generate a specific frequency signal for modulation. The main design methods of the NCO include the CORDIC algorithm and lookup table method. The CORDIC algorithm method only includes addition, subtraction, and shift operations and consumes less register resources, but the precision of the output sine and cosine values is limited by the number of iterations.

While the look-up table method consumes more resources, it has a simple structure and can generate high-quality sine and cosine waveforms. This design has high requirements on running speed and resolution. Therefore, we chose the lookup table method to realize the design of the NCO, as shown in Fig. 10.

The NCO module consists of two D flip-flops, an adder, and a sine and cosine lookup table. The input frequency control word FSW drives the accumulation of phase increments, and the phase increment values are used as address lines to read the data in the sine and cosine lookup table and return all the way back to the phase accumulator for accumulation. Based on the requirements of the TIADC system, the depth of the design is 4096, and the bit width is 18 bits.

Before decimation, the input signal should be firstly modulated with a signal from the NCO by a mixer, the spectrum of the original signal is shifted to the left and right sides based on the frequency of the modulated signal, and the process of spectrum shifting is shown in (11).

Since the working speed of the multiplier is greatly affected by layout and routing of the FPGA board, in this design, the maximum speed of a multiplier of more than 18 bits is below 450 MHz, so the multiplier needs to be optimized. We realized the mixer by using a base 4 booth encoding ^[17-19], a 4-2 compressor, and a carry save adder (CSA). The implementation block diagram is shown in Fig. 11. PP0-PP8 are nine groups of partial products and are generated by extending the lowest bit of the data by adding zero. They multiply the input signal with adjacent three-bit groups, the middle bit of the partial product is 2n, and n is 0 to 8. Since the binary number is 0 or 1, a three-digit lookup table can be quickly listed, and the operation on the multiplier can be quickly determined based on the three-digit value of the multiplier.

In this way, the 18* 18 multiplier used in the end can be reduced by half, and then an addition tree is constructed in the form of 4-2 compressors and CSA adders. The sum of partial products is sent to the 4-2 compressor or CSA adder in a group. Finally, the data is compressed into two sets of numbers C and D with a weight value and then sent to the next level of the compressor. Here, a pipeline is inserted between each stage, and these two sets of data are added to obtain the corresponding product.

After mixing, a decimation filter bank consisting of three HB filters cascaded was designed to filter and decimate data as shown in Fig. 9. Since the passband and stopband of the HB filter are symmetrical about one-half the Nyquist frequency, and nearly half of the coefficients are exactly zero, it is very suitable for use as an antialiasing filter in double sampling rate conversion.

For a cascaded system of multiple decimation filters with adjustable decimation multiples, the filtering performance of the previous decimation filter can be appropriately reduced. Th unfiltered spurs are folded into the pass band or transition band, but they can be filtered out by the last HB filter. In this way, the hardware consumption of the previous HB filter can be reduced. The spectrograms of three HB filters designed based on this standard are shown in Fig. 12. The passband ripple of the filter is not more than 0.001 dB, and the stopband suppression is not less than 100 dB.

For the design of the HB filter, multiphase structures can be accomplished by Noble's identity ^[20]. Since the HB filter has an even symmetry relationship between tap coefficients, there is partial redundancy in the traditional structure, so when designing the HB filter, we adopt a folding method, adjust the order of multiplication and addition in advance, control the scaling of the data, and avoid overflow. The 10th-order HB3-FIR filter is shown in Fig. 13, where z$^{-1}$ is the delay unit under the system clock, and D is the delay unit after division by two.

It needs to be pointed out that after modulation and filtering, a gain module is required to compensate for the half attenuation of the input signal amplitude. When only one channel of data output is desired, an I/Q two-channel signal can also be synthesized after up conversion by f$_{s}$/4 through the complex-to-real conversion function. The reason for using a signal with frequency of f$_{s}$/4 for up conversion is that the modulation process can be realized by periodically changing the symbol of the I/Q data during up conversion, thereby reducing the hardware consumption of the system.

Fig. 9. Architecture of the proposed DDC circuit.

Fig. 10. Architecture of the proposed NCO circuit.

Fig. 11. Architecture of the proposed improved mixer.

Fig. 12. The spectrum of HB filters.

Fig. 13. Architecture of the proposed HB3 filter.

5. Simulation and Verification Results

5.1 Simulation Results

The overall calibration structure was firstly verified in MATLAB. A 14-bit TIADC composed of four channels was modelled. In actual TIADCs, the time error is generally 5‰ to 1%, and the gain and offset error is generally about 1% to 6% based on a manufacturing process error statistic, so the timing error, offset error, and gain error of the sub-ADC channels were set as [2, -1, 4, 3] ‰T$_{\mathrm{s}}$, [-0.02, 0.03, 0.015, -0.01], and [0.01, 0.02, 0.025, -0.02], respectively. The iteration step value is $\mu $=2$^{-13}$.

By inputting a set of multi-frequency signals in the baseband, the calibration ability of the derivative filter under different orders was verified, and the simulation result is shown in Fig. 14. When the filter derivative is 32, the SFDR of the calibrated spectrum basically reaches the optimal value. When designing the Hilbert filter, its order is usually set to be the same as the derivative filter, so both filters’ derivatives in this paper are 32.

The calibration results in the first and second Nyquist bands are shown in Fig. 15. It is clearly seen that the SFDR and SNDR of the calibrated signal are significantly improved. Before calibration, the SFDR is about 31 dB, and the SNDR is about 30 dB. After calibration, the SFDR is about 103 dB, and the SNDR is about 85 dB.

Fig. 16 shows the output spectrum of the 4-channel TIADC with an 8-tone input signal. The lowest frequency is f$_{L}$=0.05f$_{s}$, the highest frequency is f$_{H}$=0.19f$_{s}$, and the frequency interval is about 0.02f$_{s}$. Comparing the spectrograms before and after calibration, it can be observed that spurs due to mismatches are suppressed significantly, and the dynamic performance of the system is greatly improved. With test signals in the first and second Nyquist bands at 0.3f$_{s}$ and 0.7f$_{s}$, respectively, the simulation results of signals at special frequencies are shown in Fig. 17.

Comparing the dynamic performance of the TIADC before and after calibration, it can be seen that the SFDR and SNDR are both greatly improved, which indicates the effectiveness of the proposed calibration technique. But the second Nyquist calibration may not be as good as the first one, and the reason is that the estimated error values are correlated with the input signal frequency. The higher the input signal frequency is, the bigger difference in estimated error from the actual error is, which results in a decrease of the compensation effect.

For the simulation of the DDC circuit, since the I /Q output of the DDC circuit contains the same signal information, we only show the spectrum of I in the following. Taking a signal frequency 392.11 MHz as an example, with a modulation signal at 190 MHz, according to modulation formula (11), it can be known that after modulation, the left and right spectra of the signal are at.22.11 MHz and 202.11 MHz, respectively, as shown in Fig. 18. The modulated output signal is first filtered and decimated through the first stage HB3 filter. Since the normalized band frequency of the HB3 filter is 0.9${\pi}$, which is 252 MHz, it is impossible to completely suppress the high-frequency signal. Therefore, its spectrum is folded into the transition band after the decimation. After the first decimation, the Nyquist band changes from 0-280 MHz to 0-140 MHz, the spectrum at 202.11 MHz is mirrored to 77.89 MHz, which is shown in Fig. 19.

After the 2x decimation is completed, the 4x decimation of the signal is completed using the second-stage HB2 filter. The 4x decimated spectrogram is shown in Fig. 20, where the first Nyquist band becomes to 0-70 MHz, and the undefined high-frequency part is folded to 62.11 MHz. Since the normalized stopband frequency of the last-stage HB1 filter is 0.6${\pi}$, at this time, spurs other than at 32 MHz are filtered out by HB1, and the final completed spectrogram is shown in Fig. 21.

Fig. 14. The relationship between the order of the differentiator and the SFDR after calibration.

Fig. 15. SFDR and SNDR before and after calibration.

Fig. 16. Spectrum before and after calibration with multi-tone input.

Fig. 17. (a) SFDR; (b) SNDR before and after calibration at special frequency.

Fig. 18. Spectrum of I signal after modulation.

Fig. 19. Spectrum of I signal after decimation 2 times.

Fig. 20. Spectrum of I signal after decimation 4 times.

Fig. 21. Spectrum of I signal after decimation 8 times.

5.2 Hardware Validation

A test platform was built as shown in Figs. 22 and 23. A TIADC chip was designed in a TSMC-28-nm CMOS process with a structure composed of a 14-bit, 360-MHz, four-channel TI-SAR ADC. The calibration algorithm and DDC circuit were executed in an FPGA board that houses a Xilinx FPGA chip (xczu9eg-ffvb1156-2-e).. I2C communication between the FPGA and TIADC was implemented through the FMC interface.

As the internal storage capacity of the FPGA chip is not enough, it is not able to store a large amount of the TIADC sampling data, so we used DDR4 external memory connected to the PL terminal on the ZCU102 development board to store the data acquired by the TIADC. Referring to the ZCU102 (ug1182), the DDR4 device was named MT40A256M16GE-075E, and the memory capacity was 4 Gb (256 Mb${\times}$16). Finally, all data were sent to a PC for analysis.

With a sampling frequency f$_{s}$=360 MHz and an input signal at f$_{in}$=110 MHz, the spectrum before and after calibration is shown in Figs. 24(a) and 23(b). After calibration, spurs due to channel mismatch are greatly eliminated, and the SFDR increases from 37.43 dB to 74.51 dB. The SNDR increases from 30.47 dB to 58.15 dB, which indicates the effectiveness of the proposed calibration technique.

For the DDC circuit, the verification results of the I channel outputs with 2, 4, and 8 times are shown in Figs. 25(a)-(c), respectively. The overall verification results of the calibration and DDC circuit are shown in Table 1. The FPGA verification results show that, after calibration and decimation, the spurious-free dynamic range (SFDR) improves about 30 dB, and signal-to-noise distortion ratio (SNDR) improves about 40 dB.

The characteristic comparison of the proposed calibration technique with several other calibration techniques is shown in Table 2. It which shows that the scope of application of this work is much wider, and the calibration accuracy is high. Table 3 compares the complexity of our work with the other latest calibration techniques, and it can be easily seen that the numbers of LUTs and registers of this work are the lowest, while the working frequency is the highest. The resource consumption of the filter bank of the DDC circuit is shown in Table 4. Compared with traditional and CSD techniques, the proposed CSD coding technique combined with Horner’s rule and sub-expression sharing can greatly reduce the hardware resources of the DDC circuit.

Table 1. The verification results of calibration and DDC.

	Modulation signal	SNDR/dB	SFDR/dB
Before calibration	-	30.47	37.43
After calibration	-	58.15	74.51
Decimation 2 times	100 MHz	58.22	75.12
Decimation 4 times	100 MHz	60.52	76.01
Decimation 8 times	100 MHz	62.18	78.39

Table 2. Comparison with the state-of-art calibration techniques.

Characteristic	[2]	[7]	[8]	[21]	This work
Resolution	11 bits	14 bits	8 bits	11 bits	14 bits
λfs/2M	no	no	no	no	yes
Mismatch Type	time	time gain offset	time gain offset	time gain	time gain offset
Any NBs	yes	yes	yes	yes	yes
M (# of channels)	4	2M	M	M	2M

Table 3. Comparison of hardware resources of calibration techniques.

Characteristics	[2]	[7]	[8]	[21]	This work
LUTs	8779	8903	4277	6954	6468
Registers	7741	7449	2202	6053	6333
Fmax (MHz)	194	658	165	165	658

Table 4. Comparison of hardware resources of DDC.

Filter	Resource	Tradition	CSD	This work
HB3-FIR (10 taps)	LUTs	891	481	407
	Register	911	982	467
HB2-FIR (18 taps)	LUTs	1631	871	612
	Register	1760	1747	660
HB1-FIR (62 taps)	LUTs	4114	2188	1362
	Register	4537	4164	1869

Fig. 22. The physical verification platform of the TIADC system.

Fig. 23. The schematic of the verification platform of the TIADC system.

Fig. 24. The verification results of calibration circuit.

Fig. 25. The verification results of DDC circuit.

6. Conclusion

This paper presented an all-digital post-processing circuit for a high-speed and high-precision TIADC. The main innovations are as follows. Firstly, a threshold judgement module was introduced to detect the signal at a special frequency. By pre-inputting a test signal in the TIADC, the error estimation values were estimated and stored, and the stored error estimation values were extracted to compensate for errors when the input signal is at a special frequency. This calibration technique can be applied to a TIADC at any frequency and consumes much less hardware resources. The hardware consumption of filters was greatly reduced by introducing a CSD coding technique combined with Horner’s rule and sub-expression sharing. Secondly, a DDC system with an improved mixer and filter was designed to realize decimation 1, 2, 4, and 8 times. FPGA verification results showed that the proposed technique can effectively reduce the distortion caused by channel mismatch, thereby significantly improving the SNDR and SFDR of the TIADC and meeting the need for digital down conversion.