1. Introduction

Field programmable gate arrays (FPGAs) are reconfigurable hardware devices, including look-up tables and digital signal processors, that are applied to various systems such as telecommunications ^[1-4], aerospace ^[5], and systems based on neural networks ^[6-8] or radar ^[9,10]. FPGAs are used not only for implementing operators such as signal processing, but also for implementing SoC (System on Chip) ^[11]. An SoC is a system on a chip that consists of major components such as CPU, memory, and DSP on a single chip ^[12]. In particular, when configuring a data acquisition system, various functions such as signal processing and communication with other devices such as a PC are required ^[13,14]. Since the hardware and the system that controls it need to be implemented on a single chip, it is also necessary to implement the system on a SoC ^[15,16]. In addition, as the frequency band of signals has recently increased, there is a need for a data acquisition system that can receive and process signals in the RF (Radio Frequency) band ^[17,18]. Xilinx has released an RFSoC FPGA that can implement a system that receives and processes signals in the RF band on a single chip ^[19]. RFSoC FPGAs are FPGAs with RF-ADCs (Analog-to-Digital Converters) and RF DACs (Digital-to-Analog Converters) that can transmit and receive analog signals in the RF band while enabling SoC implementation using ARM cores ^[19]. RFSoC FPGAs are categorized into Gen1, Gen2, and Gen3 based on the signal frequency bands they can receive. The Gen1, Gen2, and Gen3 RFSoC FPGAs can transmit and receive signals in the 4GHz, 5GHz, and 6GHz bands, respectively, and the sampling rate supported increases as the frequency band increases, up to 5GSPS.

Most data acquisition systems are based on SoCs, and even when using RFSoC FPGAs, the data acquisition part and the signal processing part are combined into one chip, so the data acquisition system is designed as an SoC. Because SoC design requires not only hardware design but also software design to drive the hardware, RFSoC FPGA-based data acquisition systems also require both hardware and software designs.

This paper presents a hardware and software co-design method for implementing a data acquisition system based on an RFSoC using an FPGA. The core used in the SoC is a Cortex-A53 included in Zynq UltraScale+ MPSoC (Multiprocessing SoC) ^[20], and an RF-ADC ^[21] inside the FPGA is used to digitize the analog signal. In other words, we show how to design a single chip to convert the analog signal to digital signal, process the signal processing, and deliver the result to a PC. We want to emphasize that the contribution of this paper is to present a design methodology for a high-speed signal acquisition platform from analog signal acquisition to digital signal processing on a single chip utilizing RFSoC FPGAs. Commercial products for data acquisition also utilize FPGAs and there are a number of them ^[22-24]. These products are configured to perform signal processing based on the FPGA, making the design inherently modifiable and changeable. However, commercial products do not provide internal source code, making it impossible for users to modify or change the design to suit their system without manufacturer support. The design method proposed in this paper uses RFSoC FPGAs to implement an ADC, FPGA, and SoC all on a single chip, allowing users to design a signal acquisition and processing platform that meets their requirements. In addition, signal processing and AI operations, including various types of filtering in the programmable logic of FPGA, can be implemented within the DSP block of FPGA, and SoCs can be used to support high-speed communication such as Ethernet. In summary, the advantage of this design is that it is more flexible than commercial products in responding to various design needs.

The rest of this paper is organized as follows: Section 2 shows the internal structure of the RFSoC FPGA and RF ADC/DAC. Section 3 describes the data acquisition system design methodology using both hardware and software co-design. Section 4 shows the experimental results using ZCU208 evaluation board ^[25], and Section 5 summarizes the conclusions of this paper.

2. Background

2.1. RFSoC FPGA

An RFSoC FPGA ^[19] is an FPGA that contains an SoC and RF-ADC/DAC inside the FPGA, and its internal structure is shown in Fig. 1. The inside of the FPGA is mainly divided into PS (processing system), where the SoC is implemented, and PL (programmable logic), which contains the RF-ADC/DAC.

The SoC implemented in the PS part is based on ARM Cortex-A53 processor, Cor-tex-R5, and HSSIO (High Speed Select IO). The Cortex-A53 is an APU (application processing unit) based on the 64-bit ARM v8 architecture, and the Cortex-R5 is RPU (real-time processing unit) that supports real-time processing based on the 32-bit ARM v7 architecture ^[20]. The APU of PS unit is quad-core and the RPU is dual-core. The APU or RPU can control the MIO (multiplexed IO) of the PS part, and the MIO supports communication interfaces such as CAN, SPI, I2C, USB3.0, and UART. The PS part also includes a DDR controller to control DDR memory and connectivity, a PMU (Platform Management Unit) to manage all power within the FPGA device, and a CSU (Configuration Security Unit) to manage secure boot and on-chip security ^[20].

Fig. 1. RFSoC FPGA internal structure.

Except for the cores and MIOs that make up the SoC, the rest of the programmable logics are organized in PL part. Programmable logic includes BRAM (Block RAM), DSP (Digital signal processor), CLB (Configurable logic block), IOI (Input/Output Interface), CMT (Clock Management tile), and RF-ADC/DAC. The BRAM, DSP, CLB, IOI, and CMT, which are also included in general FPGAs, have the same roles and internal structure as general FPGAs, but RF-ADC/DAC ^[21] is included only in RFSoC FPGAs.

2.2. RF-ADC/DAC

The internal structure of an RF-ADC ^[21], which is essential for receiving analog signals, includes an ADC and a DDC (Digital Down Converter), as shown in Fig. 2(a). The DDC includes a decimation filter, NCO (Numerically Controlled Oscillator), QMC (Quadrature Modulation Correction), FIFO (First-In First-Out) buffer, and threshold detector. When an analog signal is input to the RF-ADC, it first passes through a DSA (digital step attenuator), which adjusts the voltage of the input signal to a range that the ADC can recognize. The output of the DSA is then fed into the ADC and digitized into a 14-bit value. The digitized data is then processed through a digital datapath, including a DDC. In addition to the DDC, the digital datapaths include a threshold detector to check if the ADC output has crossed a threshold, a QMC to compensate for gain and phase errors, a mixer, a decimation filter, and a FIFO buffer. The mixer supports two types of mixer: coarse mixer and fine mixer. The coarse mixer handles carriers at 0, Fs/2, Fs/4, –Fs/4, and –Fs/2, while the fine mixer can mix signals at arbitrary frequencies. If the signal needs to be down sampled or filtered after mixing, it passes through a decimation filter. The filter response depends on the decimation factor and is implemented using a FIR filter. After processing through the ADC and DDC, the data is stored in the FIFO buffer. When 16 samples are collected to fill the 256-bit FIFO, the data is clock synchronized and output from the ADC. Each sample is 16 bits, organized as {2’b00, 14-bit data}.

The RF-DAC ^[21] accepts 256-bit data consisting of 16 samples, which is stored in a FIFO as shown in Fig. 2(b), and then processed through the DUC (Digital Up Converter) and DAC to output an analog signal. The data input to the DAC is also composed of 16 bits per sample, and the most significant two bits are filled with zeros. The DUC includes a FIFO, an interpolation filter, a mixer, a QMC and delay, and an output filter. The interpolation filter is needed to up sample and filter the signal. The mixer included in the DUC can use either a coarse or fine mixer, and the carrier is selected in the same way as the mixer in the DDC to design the mixer. If coarse delay adjustment is needed, the QMC is used to compensate the signal. When the sampling rate is high, the DUC is bypassed or the signal goes through the DUC but uses an IMR (Image Rejection) filter at the last stage. The IMR factor determines the order of the filter used. After passing through the DUC, the signal is input to the DAC, where it is converted to an analog signal and finally passed to the output of the DAC.

Fig. 2. Block diagram of (a) RF-ADC and (b) RF-DAC.

3. HW/SW Co-design Method

To build a data acquisition system using RFSoC FPGAs ^[19], it is necessary to design hardware using both ARM core of PS part ^[20] and the RF-ADC/DAC of PL part ^[21], and to design software using ARM core to drive the hardware of PL part. Fig. 3 shows a flow chart of the process for the hardware and software co-design. The first step in the hardware design phase is to create a block design for signal reception using Vivado Design Suite. The block design includes the IP using the RF-ADC hardware and the MPSoC IP used to implement the SoC as shown in Fig. 4. After that, it is necessary to create an HDL wrapper that is the form in which the block design containing the settings and connections is converted into HDL. The HDL wrapper is used to synthesize and implement the design on the FPGA. Then, a constraint file, XDC (Xilinx Design Constraint) file ^[26], is created and combined with the hardware design to perform the synthesis and implementation of the circuit. Note that, XDC file contains constraints for the hardware design such as timing constraints and location and pin allocations. When all the hardware mapping information is determined through implementation, a bitstream file is created that is used to program the FPGA. The bitstream file that expresses the implementation results in bitstream format. However, an SoC implementation requires not only hardware, but also software. It requires hardware design information for software development, which is why hardware extraction is performed at the end of hardware development to allow it to be used in software design.

Fig. 3. Flow chart of HW/SW co-design.

Software development utilizes Vitis IDE (Integrated Design Environment), which supports Xilinx FPGAs. The first step is to create a platform with the hardware information. The platform is prepared for the software design. Next, an application project is created to facilitate software design on the platform. Once the application project is established, the software is designed to control the hardware, as shown in Fig. 4. Fig. 4 is composed of multiple IPs (intellectual properties) that provided by Xilinx such as RFDC (RF Data Converter) IP ^[21], DMA (Direct Memory Access) IP ^[27], etc. Note that RFDC IP is implemented on RF-ADC/DAC to conduct signal converting. The software, based on the hardware in Fig. 4, include controlling the RFDC (RF Data Converter) ^[21] and DMA (Direct Memory Access) ^[27] and determining the values that need to be transmitted to CLK104 ^[28] that generates the clocks for the RF-ADC/DAC.

Once the hardware and software development are completed, it is necessary to program FPGA to verify the operation and verification of the designed system. When verifying the system, the operation of RF-ADC ^[27], and other components is checked through step-by-step debugging using the UART ^[20] inside the MPSoC.

3.1. Hardware Design

The hardware design for receiving signals through the RF-ADC can be designed using a block design, as shown in Fig. 4. The block design includes RFDC IP for receiving RF band signals ^[21], DMA ^[27] for passing RFDC results to DDR memory, Zynq UltraScale+ MPSoC IP ^[20] as the core for the SoC implementation, and AXI interface IP ^[29] for connecting the core and peripherals.

Fig. 4. Block design for data acquisition system on RF SoC FPGA.

RFDC IP ^[21] is configured inside the FPGA, and information such as the number of channels, mixer type, and clock source connection is set through IP settings as shown in Fig. 5. Fig. 5(a) shows the Basic tab to set the design information of the RF-ADC/DAC, and the clock source required to operate the RFDC IP is set through the System Clocking tab as shown in Fig. 5(b) ^[21]. The sampling clock is generated and used by the PLL inside the RF-ADC. The clock source generated by CLK104 is input to the PLL as reference clock, which the PLL uses to generate a sampling clock and input to the ADC clock. At this time, since the operating clock of the logic connected to the RFDC IP operates with the clock of the RFDC IP, the ADC clock output from the RFDC IP needs to be applied to them.

The output data of the RFDC IP is output through the AXI stream interface ^[21], which is the path shown in red in Fig. 4, so it is stored in the DDR memory through the DDR controller of the core via DMA ^[27]. Therefore, the output of the DMA is connected to the MPSoC IP, which is the core, through the AXI interface. The input and output of the DMA is also the path through the output of RFDC IP ^[21], so the ADC clock is connected and designed to operate in synchronization with the RF-ADC.

Additionally, RFDC IP ^[21], MPSoC IP ^[20], and DMA IP ^[27], AXI GPIO IP ^[30], and Clocking Wizard IP are connected as shown in Fig. 4. The hardware works as follows; First, the AXI GPIO IP carries the signals that allow the CLK104 ^[28] to operate, and the signals it carries are determined by software. The Clocking Wizard IP ^[31] uses clock dividing to generate clocks of the appropriate frequency that is applied to all logic.

Fig. 5. (a) Basic configuration and (b) system clocking configuration of RFDC IP [21].

3.2. Software Design

The software that is implemented on the core for an SoC includes control of all hardware connected to the core. In the case of Xilinx, if the design includes IPs that are provided by Xilinx, Xilinx provides APIs in C or C++ that is used to control each of the IP provided. Additionally, examples that can be designed using the functions included in each API are provided.

The hardware in the block design in Fig. 4 and the software that creates the values that need to be transmitted to the CLK104 ^[28] are organized into the flow chart shown in Fig. 6. First, the UART for debugging and sending data to the PC is initialized. Then, it also initializes the RFDC IP ^[21] and DMA IP ^[27], which are used to receive data and store it in memory. To initialize CLK104 ^[28] and generate a clock at a specific frequency, the ‘xrfclk’ API designed for CLK104 control is used. Using the ‘xrfclk’ API, the values to be transmitted to CLK104 for setting the desired frequency are created ^[28]. Using the ‘xgpio’ API, control of the AXI GPIO IP ^[30] is established to output these values through GPIO pins to CLK104 ^[28]. After completing the configuration of CLK104 ^[28], the ‘xrfdc’ API is employed to receive results from the RF-ADC ^[21] and store them in DDR memory. Once data reception is finalized, the received results are transmitted to a PC via UART ^[20]. The UART serves not only for transmitting results to the PC but also for logging output during the debugging process.

Fig. 6. Flow chart of software on ARM core.

4. Experimental Results

To verify the high-speed signal reception system utilizing the RFSoC FPGA designed in this paper, the ZCU208 evaluation board equipped with the ZU48DR, a Gen3 Zynq RF SoC FPGA, is used ^[25]. The daughter boards used to connect analog signals and generate reference clocks for ADC sampling are the XM655 ^[25] and CLK104 ^[28], as shown in Fig. 7. The XM655 daughter board ^[25] does not require any special hardware or software design configuration; it is simply connected to the evaluation board as shown in Fig. 7. The signal input through the XM655 daughter board ^[25] is varied from 10 MHz to 500 MHz, and the input signal is generated with a signal generator. The CLK104 is designed to take a 10 MHz input and generate a clock of 122.88 MHz via software. In the hardware design to enable the RF-ADC to operate at 1.96608 GSPS, the RFDC IP ^[21] uses the internal PLL to input 122.88 MHz and configure the system clocking to enable 1.96608 GSPS.

Fig. 7. Experimental environment.

Table 1 shows the hardware utilization when implementing the hardware depicted in Fig. 4 on ZU48DR. In Table 1, IO refers to inputs and outputs excluding those related to RF-ADC/DAC. Three IO components are utilized, which are GPIOs connected to CLK104 ^[28]. The RFDC IP ^[21] supports both RF-ADC/DAC functionalities, with RF-ADC/DAC utilization in Table 1 being 100%.

Following the completion of hardware and software implementation, the data acquisition system verified with the evaluation board. The designed system is employed to receive signals, and the results are transmitted to a PC for verification of signal reception. The frequency of the input signal is set to 10 MHz, 20 MHz, 50 MHz, 100 MHz, 200 MHz, 500 MHz, and Fig. 8 shows the result of sampling the input signal at 1.96608 GSPS for each frequency.

Fig. 8. Data acquisition result of (a) 10 MHz, (b) 20 MHz, (c) 50 MHz, (d) 100 MHz, (e) 200 MHz, and (f) 500 MHz signals.

These results confirm that the designed hardware and software effectively receive input signals up to 500 MHz when sampling at 1.96608 GSPS. To build a data acquisition system using RF SoC FPGAs ^[19], it is necessary to de-sign hardware using both the ARM core of PS ^[20] and the RF-ADC/DAC of PL ^[21], and to design software using the ARM core to drive the

5. Conclusion

This paper demonstrates how to design a hardware and software co-design data acquisition system using RFSoC FPGAs. Experiments are being performed using an evaluation board equipped with a Gen3 RFSoC FPGA and a daughter board that is connected to it. The experiments show that it is possible to acquire data up to 500 MHz band while supporting sampling at 1.96608 GSPS. Since the FPGA acquires analog signals and stores data after ADC processing, it performs signal processing operations such as FFT on a single chip without requiring a separate signal transmission process ^[32]. Therefore, when data acquisition in the RF band or acquisition in the hundreds of MHz to several GHz bands is necessary, it is feasible to implement ADC and digital signal processing circuits on a single chip using an RFSoC FPGA. Moreover, hardware for high-speed interfaces such as Ethernet ^[33] can be implemented on the FPGA to facilitate connections to PCs or other FPGA devices. The system designed according to the proposed method can be applied to systems requiring multi-channel data acquisition, such as image processing ^[34-36].