| Title |
Design and Analysis of a Low-cost Approximate Adder with OR and Zero Truncation |
| Authors |
(Hyoju Seo) ; (Jungwon Lee) ; (Donghui Lee) ; (Beomjun Kim) ; (Yongtae Kim) |
| DOI |
https://doi.org/10.5573/IEIESPC.2021.10.4.309 |
| Keywords |
Approximate adder; Approximate computing; Low-cost; Zero truncation; Lower-part OR truncation adder (LOTA) |
| Abstract |
This paper proposes a new cost-effective approximate adder that exploits OR operation and zero truncation. The proposed approximation technique reduces the hardware cost significantly while maintaining comparable computation accuracy. The proposed adder achieved 48%, 51%, and 48% reductions in the area, delay, and power, respectively, compared to a traditional adder when implemented in 32-nm CMOS technology. The proposed design could also enhance the normalized mean error distance up to 29% compare to the approximate adders considered in this paper. The adder showed an excellent tradeoff performance between the hardware and computation accuracy.
Furthermore, the proposed adder was adopted in a digital image processing application, and the benefit of the proposed adder is demonstrated. |