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Title Hardware Implementation of the Simplified Digital Spiking Neural Network on FPGA
Authors Phauk Sokkhey;Takeo Okazaki
DOI https://doi.org/10.5573/IEIESPC.2019.8.5.405
Page pp.405-414
ISSN 2287-5255
Keywords Spiking neuron models; Image classification; Hardware synthesis; FPGA; Verilog HDL
Abstract Artificial neural networks (ANNs) are being studied in various fields. However, classic ANNs have limitations in hardware implementation, due to computational complexity. On the other hand, spiking neural networks (SNNs), which are inspired by biological neural systems, have optimal characteristics in hardware implementation. In the SNN, communication is performed between neurons by using spikes, which are represented by a single bit. This reduces computational complexity and logic occupation in a device. SNNs have weights and delays as adjustable parameters, and have been successfully used for image classification. Although there are several mathematical spiking neuron models, to reduce computational complexity, this paper proposes a simplified and digital leaky integrate-and-fire (SDLIF) model, which is computationally efficient and powerful. Temporal coding is used as neural coding. We also describe a field-programmable gate array (FPGA) implementation using Verilog hardware description language (HDL), and discuss simple image pattern classification problems as verification. The final results demonstrate not only the performance of the SNN for image pattern recognition and classification, but also its efficiency, such as low logic occupation in the device, and low power consumption on the FPGA.